The purpose of Analog and Digital VLSI Circuit Design is to provide in a single volume a comprehensive reference work covering the broad spectrum of VLSI technology. It is written and developed for the Electronics and Communication Engineers in WBUT. The goal is to provide the most up-to-date information in IC technology, devices and their models, circuit simulations, amplifiers, logic design, memory, Switched Capacitor Circuits, ASIC. This book is not an all encompassing digest of everything taught within an Electronics Engineering curriculum on VLSI technology. It is an outcome of my experience in teaching this course. I appreciate my students who have recharged my energy in each semester with their suggestions and criticism. Chapter 1 describes the Introduction to ASIC Design, Design Strategies: Hierarchy, Regularity, Modularity & Locality and Chip Design Options: Gate Array, Field Programmable Gate Array, PLA, PLD, Standard Cell, Full Custom Design. The text has been divided into ten chapters. Chapter 2 describes Fabrication & Layout of CMOS, Fabrication Process Flow: Basic steps CMOS n-Well Process, Layout & Design Rules, CMOS inverter Layout Design. Chapter 3 describes MOS Inverter Characteristics including Transfer Characteristics: MOS with resistive load, n-MOSFET Load (Enhancement & Depletion), CMOS inverter and Transient Analysis of CMOS Inverter and Delay analysis. Chapter 4 describes the Static CMOS logic circuits which include different static VLSI logic design styles and DCVSL logic style. Chapter 5 describes the dynamic logic design styles including Domino CMOS Logic and NORA Logic. Chapter 6 describes the Sequential CMOS logic circuits including Behaviour of Bi-stable elements, SR Latch Circuit, Clocked JK Latch/Master-Slave JK. Chapter 7 describes the Subsystem Design including Adders: Carry ahead adder, Manchester carry chain, Multipliers: Serial-parallel Multiplier, array multiplier and High Density Memory: ROM, Static RAM, Dynamic RAM, SD RAM, Flash Memory. Chapter 8 describes the Physical Design including Floor Planning Methods: Block Placement & Channel Definition, Global and Channel Routing. Chapter 9 describes the Analog VLSI design including MOS Switches, Voltage follower, CMOS Current Sources and sink, CMOS Differential Amplifier and CMOS Operational Amplifier. Chapter 10 describes the Resistor realisation using Switched Capacitor, Switched Capacitor Integrator and Switched Capacitor Filters. I have tried very hard to eliminate the errors in the book, but realize that few may be slipped through. After completing many readings of the final manuscript, I think that I have corrected most of the major errors and hope that the remaining ones are relatively minor in nature. I apologize in advance for those I have missed.
Additional Info
  • Publisher: Laxmi Publications
  • Language: English
  • ISBN : 978-93-5138-249-2
  • Chapter 1

    INTRODUCTION TO ASIC Price 2.99  |  2.99 Rewards Points

    ASIC — Application Specific Integrated Circuits (ASICs) refer to those integrated circuits specifically built for specific tasks. There are many advantages of ASICs as mentioned below : • Increased speed • Lower power consumption • Lower cost (for mass production) • Better design security (difficult reverse engineering) • More compact board design (less complex PCB, less inventory costs). However, there are some disadvantages : • Long turnaround time from silicon vendors (several weeks) • Expensive for low-volume production • Very high NRE cost (high investment in CAD tools, workstations, and engineering manpower) • Once committed to silicon the design cannot be changed
  • Chapter 2

    ASIC DESIGN RULES Price 2.99  |  2.99 Rewards Points

      — For an n-well process the starting point is a p-type silicon wafer : — wafer typically 75 to 300 mm in diameter and less than 1 mm thick.   — A single p-type single crystal film is grown on the surface of the wafer by • subjecting the wafer to high temperature and a source of dopant material — The epi layer is used as the base layer to build the devices.    !" — PMOS transistors are fabricated in n-well regions — The first mask defines the n-well regions — N-well’s are formed by ion implantation or deposition and diffusion — Lateral diffusion limits the proximity between structures
  • Chapter 3

    INVERTER Price 2.99  |  2.99 Rewards Points

    The inverter is universally accepted as the most basic logic gate doing a Boolean operation on a single input variable. Figure 3.1 depicts the symbol, truth table and a general structure of a CMOS inverter. As shown, the simple structure consists of a combination of an pMOS transistor at the top and a nMOS transistor at the bottom.
  • Chapter 4

    STATIC VLSI DESIGN Price 2.99  |  2.99 Rewards Points

    There are numerous circuit styles to implement a given logic function. As with the inverter, the common design metrics by which a gate is evaluated are area, speed, energy and power. Depending on the application, the emphasis will be on different metrics, by which a gate is evaluated. For example, the switching speed of digital circuits is the primary metric in a high performance processor, while in a battery operated circuit, it is energy dissipation. Recently, power dissipation also has become an important concern and considerable emphasis is placed on understanding the sources of power and approaches to dealing with power. In addition to there metrics, roburtness to noise and reliability are also very important considerations.
  • Chapter 5

    DYNAMIC VLSI DESIGN Price 2.99  |  2.99 Rewards Points

    In the static CMOS logic with a fan-in of N requires 2N devices. A variety of approaches were presented to reduce the number of transistors required to implement a given logic function including pseudo-nMOS, pass-transistor logic. etc. For the pseudo, nMOS logic, there are (N + 1) no of transistor required to implement an N input logic gate, but it has static power dissipation. To avoid this static power dissipation and obtaining the same result, the alternating approach is called the dynamic logic design. With the addition of a clock input, it uses a sequence of precharge and conditional evaluation phase. There are different style to design a dynamic VLSI circuits: (i) Precharge evaluation logic style. (ii) Dynamic TG logic style. (iii) Pass transistor logic style. (iv) Domino logic style. (v) NORA logic style.
  • Chapter 6

    SEQUENTIAL LOGIC CIRCUIT DESIGN Price 2.99  |  2.99 Rewards Points

    If we neglect the propagation delay time, the output of the combinational logic circuit, at any given time point are directly determined as Boolean function of the input variables applied at that time. Thus, the combinational circuits lack of the capability of storing any previous events, or displaying an output behaviour which is dependent upon the previously applied inputs. The sequential circuit gives the output, which is determined by the current inputs as well as the previously applied input variables. Bistable circuits have, as their name implies, two stable stages or operation modes, each of which can be attained under certain input and output condition. Monostable circuits, have only one stable operating point (state). All basic Latch and flip-flop circuits, registers and memory elements used in digital systems fall into this category.
  • Chapter 7

    ARITHMATIC SUBSYSTEMS Price 2.99  |  2.99 Rewards Points

    The linear growth of adder carry delay with the size of the input word may be improved by calculating the carries to each stage in parallel. The carry of the ith stage, Ci may be expressed as, Ci = Gi + Pi . Ci – 1 ...(i) where Gi = Ai . Bi generate signal ...(ii) Pi = Ai ⊕ Bi propagate signal ...(iii) Expanding this, we get, Ci = Gi + Pi Gi – 1 + Pi Pi – 1 Gi – 2 + ....... + Pi Pi – 1 ...... P1 C0 ...(iv) The sum Si is generated by Si = Ci – 1 ⊕ Ai ⊕ Bi ...(v) if Pi = Ai ⊕ Bi For four stages of lookahead, the appropriate terms are C1 = G1 + P1C0 C2 = G2 + P2G1 + P2P1C0 C3 = G3 + P3G2 + P3P2G1 + P3P2P1C0 C4 = G4 + P4G3 + P4P3G2 + P4P3P2G1 + P4P3P2P1C0 = G4 + P4 [G3 + P3{G2 + P2(G1 + P1C0)}] ...(vi) A possible implementation of the carry gate for this kind of carry lookahead adder for 4 bits is shown in Fig. 7.1(a). Note that the gates have been partitioning to keep the number of inputs less than or equal to four. This is typical of the type of carry lookahead that would be used in a gate array or standard cell design.
  • Chapter 8

    FLOOR PLANNING ,PLACEMENT,PARTIONING,ROUTING Price 2.99  |  2.99 Rewards Points

    Floorplanning is the art of any physical design. A well thought-out floorplan leads to an ASIC design with higher performance and optimum area. Floorplanning can be challenging in that it deals with the placement of I/O pads and macros as well as power and ground structures. Before one proceeds with physical floorplanning one needs to make sure that the data used during the course of physical design activity is prepared properly. Proper data preparation is essential to all ASIC physical designs in order to implement a correct-by-construction design.
  • Chapter 9

    ANALOG VLSI DESIGN Price 2.99  |  2.99 Rewards Points

    MOS transistor that is to be used as a switch. A or B, can be the drain or the source of the MOS transistor depending on the terminal voltages (e.g., for an n-channel transistor, if terminal A is at a higher potential than B, then terminal A is the drain and B is the source terminal). The ‘ON’ resistance consists of the series combination of r0, rS and whatever channel resistance exists. Typically by design, the contribution from rD and rS is small such that the primary consideration is the channel resistant. In the ‘ON’ state of the switch the voltage across the switch should be small and Vas should be large. Therefore, the MOS device is assumed to be in the non-saturation region we know,
  • Chapter 10

    SWITCHED CAPACITOR CIRCUITS AND FILTER DESIGN Price 2.99  |  2.99 Rewards Points

    SWITCHED CAPACITOR CIRCUITS AND FILTER DESIGN

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